This book describes the design of network systems such as routers, bridges, switches, firewalls, and other equipment used in the Internet. It considers the functionality required for protocol processing, and explains how the functionality has been implemented on a range of hardware architectures. The book focuses on network processor technology, a recent development that has quickly become one of the standard tools designers use. In addition to discussing the motivation and use of network processors, the text provides an overview of network processor architectures, examines programming languages for network processors, and considers the many design tradeoffs.

     The text is intended for both professionals who are building network systems and students who are learning about network systems design. To aid professionals, the text discusses design decisions, both for network processors and for network systems. In addition, all examples used in discussions have been taken from commercially available products, and the code in the book has been tested on network processor hardware. To aid students, the book presents concepts without presuming a working knowledge of the jargon used in the industry. Both students and professionals will appreciate the glossary of terms that helps the reader navigate the maze of acronyms.

     Following a three-chapter review of protocols and an introduction to network systems, the main text is divided into three parts. The first part, Chapters 4 - 10, considers protocol processing, and covers implementations on a range of hardware architectures used in traditional network systems. The range extends from a conventional, uniprocessor system, used in low-end network systems, to a high-end, multiprocessor architecture that uses intelligent network interface cards to handle higher-speed networks. In addition, chapters in Part 1 discuss the important topics of classification and switching fabric architectures.

     The second part, Chapters 11 - 17, explores network processor technology. It examines the economic motivation for network processors, explains the possible roles that network processors fill in network systems, and discusses network processor architecture. To make the discussion concrete and demonstrate the variety of designs, Chapter 15 surveys commercially-available architectures. Chapter 16 considers languages used to program network processors, giving examples from two commercially-available classification languages: NCL and FPL.

     The third part of the text examines one network processor in detail. This version of the book uses Intel's IXP1200 as the example. The text presents details of both the multi-processor hardware architecture and software development environment that Intel supplies. After explaining the fundamental components on the Intel chip, chapters examine the programming paradigm, and describe how the software written for the IXP1200 uses the onboard processors and other components. Most important, the book contains the complete code for an example bump-in-the-wire network system.

     A Web site has been created to accompany the text:

http://www.npbook.cs.purdue.edu/

     I thank the many individuals and groups who have helped with this text and deserve credit. Agere, IBM, and Intel provided network processor hardware and software for my lab at Purdue. Chris Telfer worked tirelessly to set up the lab facilities, and wrote the code for the wwbump example. Other students, including Jing Liu, Xiaodong Li, Fan Zhang, and Shireen Javali searched literature, checked details, and commented on drafts. Om Prakash Pitta, Vasudeva Nithyananda Pai, and students in two graduate seminars inspired me by using network processors to create a variety of projects. Colleague Sonia Fahmy reviewed material on switching fabrics.

     I am also grateful for the comments and criticism from many professionals who either participate in the creation of network processors or use them to build network systems. Craig Partridge of BBN and Paul Phillips of Nauticus Networks provided general comments; Craig provided an insight on switching fabrics. Mike Hathaway of Austin Ventures gave valuable background, and suggested the division of second and third generation architectures. Dale Parson and Rob Munoz of Agere Systems offered extensive reviews, and provided details about both FPL and the Agere architecture. Mohammad Peyravian of IBM commented on the presentation of the IBM architecture. Matt Tryzna of IBM came to Purdue to conduct two classes on the IBM architecture, and also provided comments on a draft of the text. Erik Johnson and Aaron Kunze of Intel provided comments, including a critique of the example code. Paul Schmitt of Calix Networks filled in many background and hardware details, and helped me understand the history of the industry. T. Sridhar of Future Communications Software and John Lin of Bell Labs provided comments on chapters. Robert Dusek of Saint Joseph's College volunteered to manage the web site.

     Finally, I thank my wife, Chris, for her patient and careful editing and valuable suggestions that improve and polish each book.

Douglas E. Comer

January, 2003