This book describes the design of network systems such as routers, bridges, switches, firewalls, and other equipment used in the Internet. It considers the functionality required for protocol processing, and explains how the functionality has been implemented on a range of hardware architectures. The book focuses on network processor technology, a recent development that has become one of the standard tools designers use. In addition to discussing the motivation and use of network processors, the text provides an overview of network processor architectures, examines programming languages for network processors, and considers the many design tradeoffs.

     The text is intended for both professionals who are building network systems and students who are learning about network systems design. To aid professionals, the text discusses design decisions, both for network processors and for network systems. In addition, all examples used in discussions have been taken from commercially available products, and the code in the book has been tested on network processor hardware. To aid students, the book presents concepts without presuming a working knowledge of the jargon used in the industry. Both students and professionals will appreciate the glossary of terms that helps the reader navigate the maze of acronyms.      Following a three-chapter review of protocols and an introduction to network systems, the main text is divided into three parts. The first part, Chapters 4 - 10, considers protocol processing, and covers implementations on a range of hardware architectures used in traditional network systems. The range extends from a conventional, uniprocessor system, used in low-end network systems, to a high-end, multiprocessor architecture that uses intelligent network interface cards to handle higher-speed networks. In addition, chapters in Part 1 discuss the important topics of classification and switching fabric architectures.

     The second part, Chapters 11 - 16, explores network processor technology. It examines the economic motivation for network processors, explains the possible roles that network processors fill in network systems, and discusses network processor architecture. To make the discussion concrete and demonstrate the variety of designs, Chapter 15 surveys examples of commercially-available architectures that underscore the broad variety of approaches.

     The third part of the text examines one network processor in detail. This version of the book uses Agere's APP550 as the example. The text presents details of both the hardware architecture and software development tools that Agere supplies. Chapters explain the fundamental components on the Agere chip: the pattern processing engine, state engine, and traffic manager. After examining the reference platform, chapters in the section focus on programming they examine the special-purpose classification language used to program the pattern processor as well as the scripting language used to program the state engine and traffic manager. Finally, a chapter presents the complete code for an example network system (a DiffServ router) that demonstrates classification, policing, buffer management, and scheduling. The material on traffic policing, queuing, and shaping is new, and represents a major addition to the previous version of the text.

     The CD-ROM that is included with the text provides an exciting opportunity: the set of software tools on the CD-ROM allows programmers who do not have network processor hardware to create and test programs for a network processor. The CD-ROM includes all software needed: compilers that translate source programs into binary code for the Agere network processor and a simulator that interprets the code exactly like an Agere chip (at a slower speed, of course). A graphical interface tool known as the System Performance Analyzer (SPA) forms the centerpiece of the software on the CD-ROM. The SPA provides an easy interface for all tools, and allows an experimenter to create a set of packets that can be used as input to the simulator. Thus, even readers who do not have access to hardware can experience programming a network processor firsthand.

    A web site has been created to accompany the text:
The site, which is managed by Robert Dusek, contains all the program examples from the text as well as a set of course notes from Lehigh University as well as a set from the author. I invite professors to contribute notes from their courses or suggestions for teaching. In addition, I invite network processor vendors to submit example code for their chips. In particular, I encourage each vendor to show how the example system from Chapter 24 is implemented on their network processor.

     I thank the many individuals and groups who helped with the text and deserve credit. Agere, IBM*, and Intel provided network processor hardware and software for my lab at Purdue. Dan Ardelean, James Cernak, and Max Martynov researched the Agere chip, contributed ideas, and reviewed drafts of chapters; Max wrote the code for the DiffServ example. Tomasz Czajka commented on a draft. Chris Taylor helped update information on vendors. Other students, including Chris Telfer, Jing Liu, Xiaodong Li, Fan Zhang, and Shireen Javali contributed to an earlier version of the text. Students in my graduate seminars inspired me by using network processors to create a variety of projects.

     I am also grateful for the comments and criticism from many professionals who either participate in the creation of network processors or use them to build network systems. Craig Partridge of BBN and Paul Phillips of Nauticus Networks provided general comments on the first version of the book; Craig provided an insight on switching fabrics. Mike Hathaway of Austin Ventures gave valuable background for the first version. Paul Schmitt of Calix Networks filled in many background and hardware details, and helped me understand the history of the industry. T. Sridhar of Future Communications Software provided comments on the first version.

     Dale Parson of Agere provided detailed information on the Agere chip, and carefully checked the manuscript. Rob Munoz of Agere also provided comments. John Lin of Bell Labs reviewed the manuscript for technical accuracy. Simon Stanley of Earlswood Marketing provided a review. Robert Dusek of Saint Joseph's College volunteered to manage the web site.

     Finally, I thank my wife, Christine, for her patient and careful editing and valuable suggestions that improve and polish each book.

Douglas E. Comer

September, 2004

* Since the donation, IBM has sold its network processor division to Hifn, Incorporated.

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